I’m not familiar enough with how Habit and Ante represent memory allocation to say, but part of the problem right now is that there’s already a VM baked into the chip to provide the PDP-11 style emulation on top of it. Ideally, we’d want chips that expose their native behavior, and then craft languages to take advantage of it. Similarly to what we’re seeing happening with graphics chips.
Is this issue persistent in RISC-based processors too, like SPARC, POWER or RISC-V? Or is this a modular component that can go in with any architecture?
I imagine it would be the same dynamic, and you could have an emulation layer on the chip with its own instruction set for legacy code while providing direct access to the native instruction set.
I’m not familiar enough with how Habit and Ante represent memory allocation to say, but part of the problem right now is that there’s already a VM baked into the chip to provide the PDP-11 style emulation on top of it. Ideally, we’d want chips that expose their native behavior, and then craft languages to take advantage of it. Similarly to what we’re seeing happening with graphics chips.
Is this issue persistent in RISC-based processors too, like SPARC, POWER or RISC-V? Or is this a modular component that can go in with any architecture?
I imagine it would be the same dynamic, and you could have an emulation layer on the chip with its own instruction set for legacy code while providing direct access to the native instruction set.